Reed-Solomon Decoder

Reed-Solomon (RS) decoder is ideal for correcting errors that occur in clusters. Clustered bit errors are usual when there is frequency selective fading or multipath fading.

RS coding is a block coding technique. These codes are generally designated as (N,K,T) block codes. ‘K’ is the number of information symbols per block, ‘N’ is the number of symbols per block and T is the number of correctable errors.

This decoder is capable of decoding shortened and punctured codes. This can be controlled in real time allowing block by block code rate changes.

This core is written in VHDL, capable of being used on any FPGA/ASIC architecture.

Features

• Parameterisable primitive polynomial
• Parameterisable symbol size (code block length)
• Parameterisable number of correctable errors
• Parameterisable input buffer size
• Decodes shortened and punctured codes
• Fully synchronous using single clock
• User friendly interface
• Area efficient design
• Silicon verified in multiple devices
• Suitable for WMAN (802.16), DVB and other OFDM standards
• VHDL implementation allowing use in any FPGA/ASIC architecture

Deliverables

• Netlist or synthesizable RTL source code in VHDL
• Comprehensive verification test bench and vectors in VHDL
• Integration documentation and user guide